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ISL6596
Data Sheet November 2, 2005 FN9240.0
Synchronous Rectified MOSFET Driver
The ISL6596 is a high frequency, MOSFET driver optimized to drive two N-Channel power MOSFETs in a synchronous buck converter topology. This driver combined with Intersil's Multi-Phase Buck PWM controllers forms a complete singlestage core-voltage regulator solution with high efficiency performance at high switching frequency for advanced microprocessors. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6596 features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6596 also features an input that recognizes a highimpedance state, working together with Intersil multi-phase 3.3V or 5V PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage.
Features
* Drives Two N-Channel MOSFETs * Adaptive Shoot-Through Protection * 0.4 On-Resistance and 4A Sink Current Capability * Supports High Switching Frequency - Fast Output Rise and Fall Time - Low Tri-State Hold-Off Time (20ns) * Support 3.3V and 5V PWM Input * Low Quiescent Supply Current * Power-On Reset * Expandable Bottom Copper Pad for Heat Spreading * Dual Flat No-Lead (DFN) Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6596CBZ (Note) PART MARKING 6596CBZ TEMP RANGE (C) 0 to 70 PACKAGE 8 Ld SOIC PKG. DWG. # M8.15
ISL6596CBZ-T 6596CBZ (Note) ISL6596CRZ (Note) 596Z
8 Ld SOIC Tape and Reel 0 to 70 10 Ld 3x3 DFN L10.3x3
Applications
* Core Voltage Supplies for Intel(R) and AMD(R) Microprocessors * High Frequency Low Profile High Efficiency DC/DC Converters * High Current Low Voltage DC/DC Converters * Synchronous Rectification for Isolated Power Supplies
ISL6596CRZ-T 596Z (Note) ISL6596IBZ (Note) ISL6596IBZ-T (Note) ISL6596IRZ (Note) ISL6596IRZ-T (Note) 96IZ 96IZ
10 Ld DFN Tape and Reel -40 to 85 8 Ld SOIC 8 Ld SOIC Tape and Reel -40 to 85 10 Ld 3x3 DFN L10.3x3 10 Ld DFN Tape and Reel M8.15
Related Literature
* Technical Brief TB389 "PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages" * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved Intel(R) is a registered trademark of Intel Corporation. AMD(R) is a registered trademark of Advanced Micro Devices, Inc.
ISL6596 Pinout
ISL6596 (SOIC) TOP VIEW
UGATE BOOT PWM GND 1 2 3 4 8 7 6 5 PHASE VCTRL VCC LGATE 1 2 3 4 5
ISL6596 (DFN) TOP VIEW
10 PHASE 9 8 7 6
UGATE BOOT N/C PWM GND
VCTRL N/C VCC LGATE
Block Diagram
ISL6596
VCC VCTRL
BOOT UGATE SHOOTTHROUGH PROTECTION CONTROL LOGIC 7k VCC LGATE GND PHASE
7k PWM
VCTRL = CONTROLLER VCC
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FN9240.0 November 2, 2005
ISL6596 Typical Application - Multi-Phase Converter Using ISL6596 Gate Drivers
VIN +5V +3.3V +3.3V VCC VCTRL PWM1 PWM2 PWM CONTROLLER (ISL69XX) VID (OPTIONAL) ISEN1 ISEN2 +5V VIN +VCORE PWM ISL6596 PHASE LGATE BOOT UGATE RUGPH
FB VCC VSEN
COMP
PGOOD
FS/EN GND
VCC VCTRL PWM ISL6596
BOOT UGATE RUGPH
PHASE LGATE
RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS (SEE APPLICATION INFORMATION SECTION ON PAGE 8)
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FN9240.0 November 2, 2005
ISL6596
Absolute Maximum Ratings
Supply Voltage (VCC, VCTRL) . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC) . . . . . . . . . GND -8V (<20ns Pulse Width, 10J) to 30V (<100ns) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT . . . . . . . . . . . VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V . . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to 125C HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Notes 1, 2, & 3) JA (C/W) JC (C/W) SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A DFN Package (Notes 2 & 3). . . . . . . . . 48 7 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40C to 100C Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 3. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current POR Rising POR Falling Hysteresis VCTRL INPUT Rising Threshold Falling Threshold PWM INPUT Sinking Impedance Source Impedance Tri-State LowerThreshold Tri-State Upper Threshold Tri-State Shutdown Holdoff Time
These specifications apply for Recommended Operating Conditions, unless otherwise noted. SYMBOL IVCC TEST CONDITIONS PWM pin floating, VVCC = 5V MIN 2.2 2.4 RPWM_SNK RPWM_SRC VVCTRL = 3.3V (-110mV Hysteresis) VVCTRL = 5V (-250mV Hysteresis) VVCTRL = 3.3V (+110mV Hysteresis) VVCTRL = 5V (+250mV Hysteresis) tTSSHD tRU tRL tFU tFL tPDLU tPDLL tPDHU tPDHL tPTS RUG_SRC RUG_SNK RLG_SRC RLG_SNK tPDLU or tPDLL + Gate Falling Time VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded 250mA Source Current 250mA Sink Current 250mA Source Current 250mA Sink Current TYP 190 3.4 3.0 400 2.75 2.65 3.5 3.5 1.1 1.5 1.9 3.25 20 8.0 8.0 8.0 4.0 20 15 19 18 30 1.0 1.0 1.0 0.4 MAX 4.2 2.90 2.5 2.5 2.5 1.0 mV V V k k V V V V ns ns ns ns ns ns ns ns ns ns UNITS A
SWITCHING TIME (See Figure 1 on Page 5) UGATE Rise Time (Note 4) LGATE Rise Time (Note 4) UGATE Fall Time (Note 4) LGATE Fall Time (Note 4) UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay Tri-state to UG/LG Rising Propagation Delay OUTPUT (Note 4) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTE: 4. Guaranteed by Characterization. Not 100% tested in production.
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FN9240.0 November 2, 2005
ISL6596 Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check diagram for corresponding DFN pinout.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Locally bypass with a high quality ceramic capacitor to ground.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive. Connect a bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge used to turn on the upper MOSFET. See the Bootstrap Considerations section for guidance in choosing the appropriate capacitor value.
VCTRL (Pin 7)
This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for 5V PWM input.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET. This pin provides the return path for the upper gate driver current.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the Tri-state PWM Input section for further details. Connect this pin to the PWM output of the controller.
Thermal Pad (in DFN only)
The metal pad underneath the center of the IC is a thermal substrate. The PCB "thermal land" design for this exposed die pad should include vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should be either grounded or floating, and it should not be connected to other nodes. Refer to TB389 for design guidelines.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
Timing Diagram
50% of VCC PWM tPDHU tPDLU tRU tPTS 1V UGATE LGATE 1V tRL tTSSHD tPDLL tPDHL tFL tRU tTSSHD
tFU
tPTS
FIGURE 1. TIMING DIAGRAM
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FN9240.0 November 2, 2005
ISL6596
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6596 MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising transition on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications. Adaptive shoot-through circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1V. The upper gate drive then begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time, tPDHL, after the upper MOSFET's gate voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used. This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.4 on-resistance and 4A sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower MOSFET and help prevent shoot through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node. not exceed either output's turn-off propagation delay plus the MOSFET gate discharge time to ~1V. Abnormally long PWM signal transition times through the shutdown window will simply introduce additional dead time between turn off and turn on of the synchronous bridge's MOSFETs. For optimal performance, no more than 50pF parasitic capacitive load should be present on the PWM line of ISL6596 (assuming an Intersil PWM controller is used).
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size:
Q GATE C BOOT_CAP ------------------------------------V BOOT_CAP Q G1 * VCC Q GATE = ------------------------------ * N Q1 V GS1
(EQ. 1)
where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two IRLR7821 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the QGATE is calculated to be 22nC at VCC level. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.110F is required. The next larger standard value capacitance is 0.22F. A good quality ceramic capacitor is recommended.
2.0 1.8 1.6 1.4 CBOOT_CAP (F) 1.2 1.0 0.8 0.6
nC 50
PWM Input and Threshold Control
A unique feature of the ISL6596 is the programmable PWM logic threshold set by the control pin (VCTRL) voltage. The VCTRL pin should connect to the VCC of the controller, thus the PWM logic threshold follows with the voltage level of the controller. For 5V applications, this pin can tie to the driver VCC and simplify the routing. The ISL6596 also features the adaptable tri-state PWM input. Once the PWM signal enters the shutdown window, either MOSFET previously conducting is turned off. If the PWM signal remains within the shutdown window for longer than the gate turn-off propagation delay of the previously conducting MOSFET, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. The PWM rising and falling thresholds outlined in the Electrical Specifications determine when the lower and upper gates are enabled. During normal operation in a typical application, the PWM rise and fall times through the shutdown window should 6
QGATE = 100nC
0.4 0.2 20nC
0.0 0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VBOOT_CAP (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
FN9240.0 November 2, 2005
ISL6596
Power Dissipation
Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET's internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125C. The maximum allowable IC power dissipation for the SO8 package is approximately 800mW at room temperature, while the power dissipation capacity in the DFN package, with an exposed heat escape pad, is much higher. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver's internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively:
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q * VCC Q G1 * VCC 2 P Qg_Q1 = ---------------------------------- * F SW * N Q1 V GS1 Q G2 * VCC 2 P Qg_Q2 = ---------------------------------- * F SW * N Q2 V GS2 Q G1 * N Q1 Q G2 * N Q2 I VCC = ----------------------------- + ----------------------------- * VCC * F SW + I Q V GS2 V GS1 (EQ. 2)
The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as:
P DR = P DR_UP + P DR_LOW + I Q * VCC R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- * --------------------2 R HI1 + R EXT1 R LO1 + R EXT1 R LO2 R HI2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- * --------------------2 R HI2 + R EXT2 R LO2 + R EXT2 R GI1 R EXT2 = R G1 + ------------N
Q1
(EQ. 4)
R GI2 R EXT2 = R G2 + ------------N
Q2
VCC
BOOT D CGD RHI1 RLO1 G RG1 RGI1 CGS S PHASE Q1 CDS
UGATE
(EQ. 3)
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver's total quiescent current with no load at both drive outputs; NQ1 and NQ2 are the number of upper and lower MOSFETs, respectively. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible.
VCC D CGD RHI2 RLO2 LGATE G RG2 RGI2 CGS GND S Q2 CDS
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
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FN9240.0 November 2, 2005
ISL6596 Application Information
MOSFET Selection
The parasitic inductances of the PCB and of the power devices' packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs and packaging can go a long way toward minimizing such unwanted stress. The D2-PAK, or D-PAK packaged MOSFETs, have large parasitic lead inductances and are not recommended unless additional circuits are implemented to prevent the BOOT and PHASE pins from exceeding the device rating. Low-profile MOSFETs, such as Direct FETs and multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK), have low parasitic lead inductances and are preferred.
Upper MOSFET Self Turn-On Effects At Startup
Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, because of self-coupling via the internal CGD of the MOSFET, the UGATE could momentarily rise up to a level greater than the threshold voltage of the MOSFET. This could potentially turn on the upper switch and result in damaging inrush energy. Therefore, if such a situation (when input bus powered up before the bias of the controller and driver is ready) could conceivably be encountered, it is a common practice to place a resistor (RUGPH) across the gate and source of the upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage's rate of rise, the CGD/CGS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, a 5k to 10k resistor is typically sufficient, not affecting normal performance and efficiency. The coupling effect can be roughly estimated with the following equations, which assume a fixed linear input ramp and neglect the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components such as lead inductances and PCB capacitances are also not taken into account. These equations are provided for guidance purpose only. Therefore, the actual coupling effect should be examined using a very high impedance (10M or greater) probe to ensure a safe design margin.
DS --------------------------------- dV ------ R C dV iss V GS_MILLER = ------- R C rss 1 - e dt dt -V
Layout Considerations
A good layout helps reduce the ringing on the switching node (PHASE) and significantly lowers the stress applied to the output drives. The following advice is meant to lead to an optimized layout: * Keep decoupling loops (VCC-GND and BOOT-PHASE) as short as possible. * Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, GND, VCC) should be short and wide, as much as possible. * Minimize the inductance of the PHASE node. Ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. * Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. In addition, for heat spreading, place copper underneath the IC whether it has an exposed pad or not. The copper area can be extended beyond the bottom area of the IC and/or connected to buried power ground plane(s) with thermal vias. This combination of vias for vertical heat escape, extended copper plane, and buried planes improve heat dissipation and allow the part to achieve its full thermal potential.
(EQ. 5)
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
VCC
BOOT CBOOT CGD DU
VIN D
ISL6596
UGATE RUGPH
G RGI CGS S
CDS
DL
QUPPER
PHASE
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE UPPER MOSFET MILLER COUPLING
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FN9240.0 November 2, 2005
ISL6596 Dual Flat No-Lead Plastic Package (DFN)
2X A D 0.15 C A 2X 0.15 C B
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.80 NOMINAL 0.90 0.20 REF 0.18 0.23 3.00 BSC 1.95 2.00 3.00 BSC 1.55 1.60 0.50 BSC 0.25 0.30 0.35 10 5 0.40 1.65 2.05 0.28 MAX 1.00 0.05 NOTES 5,8 7,8 7,8 8 2 3 Rev. 3 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
C L
6 INDEX AREA TOP VIEW
E
A3 b D
B
D2 E E2
0.10 C
e k L
A C SEATING PLANE SIDE VIEW
0.08 C
A3
N Nd
7 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2
8
D2/2 NX k E2 E2/2
NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW 0.415 NX (b) 5 SECTION "C-C" C NX b (A1) 0.200 NX L NX b 5 0.10 M C A B
L e CC TERMINAL TIP
FOR ODD TERMINAL/SIDE
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FN9240.0 November 2, 2005
ISL6596 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN9240.0 November 2, 2005

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